The present invention relates generally to integrated circuit (IC) designs, and more particularly to a single end read module for register files.
A register file is a set of registers implemented in a central processing unit (CPU) for temporary data storage. The register file typically contains dedicated read and write ports whereas a memory device, such as random access memory (RAM), usually perform read and write functions through the same port. The register file can be accessed at a speed faster than that of the memory device, and therefore supports the CUP to function at a high speed.
FIG. 1 schematically illustrates a conventional single end read module 100 for enabling register files to be accessed from the outside for read operation. The single end read module 100 is comprised of a number of local I/O modules 102, each of which is connected to a register or memory cell. The local I/O module 102 is connected to a global bit line 106, which is further connected to an I/O pin (not shown in this figure) for data outputs, though a pull-down driver 104.
The I/O module 102 is comprised of PMOS transistors P1, P2, P3 and P4 and a NAND gate 112. PMOS transistors P1 and P2 have their sources coupled to a voltage supply VDD, and their gates controlled by a local pre-charge signal S1. The NAND gate 112 has two input terminals coupled to local bit lines 114 and 116, and an output terminal coupled to the gate of the NMOS transistor N1, which makes up the pull-down driver 104.
A latch 108 comprised of two serially connected inverters 110a and 110b is coupled to the global bit line 106 for latching a logic state of the signal thereon. A PMOS transistor P5 has a source coupled to the voltage supply VDD and a drain coupled to the global bit line 106. The gate of the PMOS transistor P5 is controlled by a global pre-charge signal S2.
In the pre-charge stage, the local pre-charge signal S1 is asserted to turn on PMOS transistors P1 and P2, thereby raising the signals on the local bit lines 114 and 116 to a high logic state. Since both input terminals of the NAND gate 112 receive high signals, the NAND gate 112 outputs a low signal, which, in turn, switches of the NMOS transistor N1. In this stage, the global pre-charge signal S2 is also asserted to turn on the PMOS transistor P5, thereby raising the signal on the global bit line 106 to a high state. The high signal on the global bit line 106 is latched by the latch 108.
In read operation, the local and global pre-charge signals S1 and S2 are disabled to allow the signals on the global bit line 106 to freely respond to the value stored in the register or memory cell (not shown in the figure) coupled to the local bit lines 114 and 116. If the voltage on either one of the bit lines 114 and 116 is low, the NAND gate 112 outputs a high signal, which, in turn, switches on the NMOS transistor N1. As the source of the NMOS transistor N1 is coupled to ground or VSS, the voltage on the global bit line 106 is pulled down, thereby causing the latch 108 to flip.
One drawback of the conventional single end read module 100 is that it is susceptible to noise-induced failure. Noise present on the global bit line 106 can cause the latch 108 to flip, thereby causing the read operation to fail. This causes reliability issues. Moreover, in a low voltage supply design, the latch 108 is even more prone to the noise-induced failure. Given the trend of low supply voltage in IC designs, failures caused by the latch 108 become a serious reliability issue.
As such, what is needed is a single end read module with improved reliability for register files.